Area-efficient designs for modern microprocessors, DSP's (Digital Signal Processors), SoC's (System-on-Chip) in wearables, IoTs (Internet-of-Things), smartphones, tablets, laptops, and servers, etc., are increasingly becoming a critical factor due to the following requirements: reducing silicon cost, decreasing PCB (Printed Circuit Board) footprint, improving time-to-market (TTM), and slower scaling cadence of process technology node. These requirements all need to be met while meeting the stringent frequency and/or performance targets and power/leakage budgets.
The standard cell and fundamental building block of any digital integrated circuit is the latch or flip-flop, which is used to store a state in any sequential logic. Each latch or flip-flop may include testability circuit hooks such as Level-Sensitive Scan Design (LSSD). These extra circuits that are only used for testing (e.g., design for test (DFT)) can consume approximately, for example, 70% of the standard cell size of a latch, therefore are a significant overhead.